Cell processors are a type of microprocessor that utilizes parallel processing. The basic configuration of a cell processor includes a “Power Processor Element” (“PPE”) (sometimes called “Processing Element”, or “PE”), and multiple “Synergistic Processing Elements” (“SPE”). The PPEs and SPEs are linked together by an internal high speed bus dubbed “Element Interconnect Bus” (“EIB”). Cell processors are designed to be scalable for use in applications ranging from the hand held devices to main frame computers.
A typical cell processor has one PPE and up to 8 SPE. Each SPU is typically a single chip or part of a single chip containing a main processor and a co-processor. All of the SPUs and the PPU can access a main memory, e.g., through a memory flow controller (MFC). The SPUs can perform parallel processing of operations in conjunction with a program running on the main processor. The SPUs have small local memories (typically about 256 kilobytes) that must be managed by software—code and data must be manually transferred to/from the local SPU memories. For high performance, this code and data must be managed from SPU software (PPU software involvement must be minimized). There are many techniques for managing code and data from the SPU. Often, different techniques for managing code and data from the SPU need to operate simultaneously on a cell processor. There are many programming models for SPU-driven task management. Unfortunately, no single task system is right for all applications.
Cell processors are used in applications such as vertex processing for graphics. The processed vertex data may then be passed on to a graphics card for pixel processing. In vertex processing, a cell processor may be called upon to draw a number of polygons. Each polygon is defined by three or more vertices. Handling of such vertex data may be problematic in situations where a large number of vertices need to be processed. For example, a cell processor may be called upon to draw 10,000 polygons. If each polygon requires three vertices the cell processor must process 30,000 vertices. If each vertex requires 32 bytes of data the 10,000 polygons will require 960 kilobytes. Unfortunately this is larger than the local storage capacity of a typical SPU (typically about 256 kilobytes).
Thus, there is a need in the art, for a method and system for distributing cell processor tasks and managing cell processor data in a way that addresses such problems.